This invention relates to polishing of semiconductor wafers and, more particularly, to compositions and methods for removing wafer layers, such as, barrier materials in the presence of another layer, such as a low-k dielectric layer.
Typically, semiconductor substrates have a silicon base and dielectric layers containing multiple trenches arranged to form a pattern of circuit interconnects within the dielectric layer. These trench patterns have either a damascene structure or dual damascene structure. In addition, typically one to as many as three or more capping layers coat the trench patterned dielectric layer with a barrier layer covering the capping layer or capping layers. Finally, a metal layer covers the barrier layer and fills the patterned trenches. The metal layer forms circuit interconnects that connect dielectric regions and form an integrated circuit.
The capping layers can serve different purposes. For example, a capping layer, such as, silicon carbide nitride coating dielectrics, may act as a polishing stop to protect underlying dielectrics from removal during polishing. The silicon carbide nitride's nitrogen concentration varies with manufacturer; and it may contain up to approximately 50 atomic percent nitrogen—if the nitride content is zero, then the stopping layer has a chemistry of silicon carbide. In addition, a silicon dioxide layer, silicon nitride layer or a combination of the two layers, may correct topography above the stopping layer. Typically, a barrier layer, such as a tantalum or tantalum nitride barrier layer, coats the capping layer and a metal conductive layer covers the barrier layer to form the interconnect metal.
Chemical mechanical planarization or CMP processes often include multiple polishing steps. For example, an initial planarization step removes a metal layer from underlying barrier dielectric layers to planarize the wafer. This first-step polishing removes the metal layer, while leaving a smooth planar surface on the wafer with metal-filled trenches that provide circuit interconnects planar to the polished surface. First-step polishing steps tend to remove excess interconnect metals, such as copper, at a relatively high rate. After the first-step polishing, a second-step polishing process typically removes a barrier that remains on the semiconductor wafer. This second-step polishing removes the barrier from its underlying dielectric layer to provide a planar polished surface on the dielectric layer. The second-step polishing may stop on a capping layer, remove all capping layers or remove some of the underlying dielectric layer.
Unfortunately, CMP processes often result in the excess removal of unwanted metal from circuit interconnects or “dishing”. This dishing can result from, both first-step polishing and second-step polishing. Dishing in excess of acceptable levels causes dimensional losses in the circuit interconnects. These thin areas in the circuit interconnects attenuate electrical signals and can impair continued fabrication of dual damascene structures. In addition to dishing, the CMP processes often remove excessive amounts of the dielectric layer in an effect known as “erosion”. Erosion that occurs adjacent to the interconnect metal can introduce dimensional defects in the circuit interconnects. Furthermore, erosion is a particular problem for low-k and ultra-low-k dielectrics. In a manner similar to dishing, these defects contribute to attenuation of electrical signals and impair subsequent fabrication of dual damascene structures.
After removing the barrier layer and any undesired capping layers, a first capping layer stop, such as a silicon carbide nitride stopping layer, often prevents the CMP process from damaging the dielectric. This stopping layer typically protects the underlying dielectrics to avoid or alleviate dielectric erosion by controlling removal rate. The removal rates of the barrier and other capping layers (such as, silicon nitride and silicon dioxide), versus, a removal rate of the stopping layer are examples of selectivity ratios. For purposes of this application, selectivity ratio refers to the ratio in removal rate as measured in angstroms per minute.
Singh et al., in WO Pat. Pub. No. 03/072670, disclose the optional use of nonionic, anionic, cationic and zwitterionic surfactants to improve selectivity. This patent publication, however, does not disclose a specific formulation useful for limiting low-k dielectric erosion.
There is an unsatisfied demand for a composition that selectively removes barrier materials and capping materials (such as, silicon nitride and silicon dioxide) without removing excessive amounts of dielectric layers, such as low-k dielectric layers. In addition, there is a need for a slurry that polishes semiconductor wafers as follows: removes barrier materials; reduces interconnect dishing, reduces dielectric erosion; avoids peeling of the dielectric; and operates with or without a silicon carbide-nitride stopping layer.